1. Field of Invention
The present invention relates to a system debugging device for debugging a system in which a plurality of bus masters mounted on a large-scale integrated circuit (LSI) share an internal bus.
2. Description of Related Art
FIG. 5 is a diagram showing an example of a technique for debugging a system, in which a central processing unit 32 (CPU) is mounted on an LSI 30 (hereinafter referred to as CPU-containing system). The CPU-containing system in FIG. 5 includes bus masters 34, such as a CPU, a direct memory access (DMA) controller 36, and other bus masters; and bus slaves 38, such as an external memory interface (I/F), an internal memory, and other bus slaves. All of the bus masters 34 and bus slaves 38 are mutually connected via an internal bus 33, and this CPU-containing system is connected via the external memory I/F to an external memory 31.
FIG. 6 is a diagram showing an example of the inner structure of the CPU-containing system in FIG. 5. For ease of explanation, the CPU 32 and the DMA controller 36 are shown as bus masters, while Slave 1, Slave 2, and Slave 3 are shown as bus slaves.
Address signals, bus control signals, and data signals outputted from the CPU 32 and the DMA controller 36 are selectively outputted from a multiplexer MUX 1, according to master selection information outputted from a bus arbiter 12 arbitrating bus ownership, and are inputted into Slave 1, Slave 2, and Slave 3, respectively. Address signals outputted from the multiplexer MUX 1 are also inputted into an address decoder 14 selecting bus slaves. Data signals outputted from Slave 1, Slave 2, and Slave 3 are selectively outputted from a multiplexer MUX 2, according to slave selection information outputted from the address decoder 14, and are inputted into the CPU 32 and the DMA controller 36.
In the CPU-containing system shown in FIG. 6, in order for the CPU 32 and the DMA controller 36, which are bus masters, to use the internal bus, the CPU 32 and the DMA controller 36 send bus request signals (not shown) to the bus arbiter 12.
When the bus request signals are received, the bus arbiter 12 selects, according to the priority of bus ownership (that is, a right to use the internal bus) at that time, a bus master having the highest priority among those that have sent bus request signals. Then, the bus arbiter 12 sends grant signals (not shown) to the selected bus master, so as to indicate that the bus ownership is granted. At the same time, the bus arbiter 12 sends master selection information for specifying the selected bus master to the multiplexer MUX 1.
Address signals, bus control signals, and data signals outputted from the bus master that has received the grant signals are then selectively outputted from the multiplexer MUX 1 according to the master selection information outputted from the bus arbiter 12.
The address decoder 14 decodes the address signals outputted from the multiplexer MUX 1 to generate slave selection signals (not shown). The slave selection signals are signals for selecting a bus slave specified by the address signals and are sent to Slave 1, Slave 2, and Slave 3, respectively. At the same time, the address decoder 14 sends slave selection information for specifying the selected bus slave to the multiplexer MUX 2.
Slave 1, Slave 2, and Slave 3 receive the slave selection signals. When one of the slaves is selected, data signals are written into the selected slave according to the address signals and bus control signals (write signals) outputted from the multiplexer MUX 1. Data signals read from the selected slave according to the address signals and bus control signals (read signals) are selectively outputted from the multiplexer MUX 2 according to the slave selection information outputted from the address decoder 14.
Then, data signals outputted from the multiplexer MUX 2 are received by the bus master that received the above-described grant signals.
When the above-described CPU-containing system is compliant with the joint test action group (JTAG) standard, debugging of the system is normally performed, as shown in FIG. 5, by connecting the CPU 32 to an in-circuit emulator (ICE) via a debugging I/F, and further connecting the ICE to a personal computer (PC), thereby monitoring the operation of the CPU 32, while controlling it, using a debugger (software program for debugging) running on the PC.
Normally, information on a stop address, which is called a breakpoint, from the debugger running on the PC is placed in user software to be debugged. When the CPU reaches the address of the breakpoint, the ICE not only stops the operation of the CPU, but also reads, if necessary, the internal states of registers and memories that are connected to an internal register and internal bus of the CPU into the PC. An operator responsible for debugging proceeds with the debugging process based on this information while monitoring the hardware status.
However, in a known debugging process for a system in which a plurality of bus masters including a CPU are mounted on an LSI, a transfer of bus ownership from the CPU to other bus masters causes debugging to stop, because the CPU cannot monitor the operation of other bus masters in this case. Specifically, the CPU cannot obtain any information, for example, as to whether or not the bus ownership is transferred to other bus masters, and if transferred, as to the size and duration of data transfer, from which bus master to which slave.
Conventional techniques related to the present invention are disclosed, for example, in Japanese Unexamined Patent Application Publication No. 63-167940 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 5-14451 (Patent Document 2).
Patent Document 1 is concerned with a multiprogramming-oriented CPU responsible for processing of an operating system to achieve multiprogramming. Patent Document 1 discloses means for outputting information concerning a multiprogramming system to an external data bus of the CPU, during execution of a system call instruction, and showing to devices outside the CPU that the information has been outputted to the external data bus.
Patent Document 2 is concerned with a line monitoring method for a data communication system that includes a line control unit performing alternate communication with external data communication devices via a transmission line and a human-machine interface unit performing input and output operations for the entire system. Patent Document 2 discloses that, in the line monitoring method, send data and receive data on an output line and an input line, respectively, in the line control unit are collected at an input/output section of the line independently of a data transmission control circuit for online operation. Also, Patent Document 2 teaches that the collected send/receive data is stored in the data communication system, and the stored send/receive data is displayed according to instructions from the human-machine interface unit.